View MSM7584CTS-K_1284769.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

E2U0046-16-X2
Semiconductor MSM7584C
Semiconductor p/4 Shift QPSK MODEM/ADPCM CODEC
This version:MSM7584C Jan. 1998 Previous version: Nov. 1996
GENERAL DESCRIPTION
The MSM7584C is a CMOS IC developed for use with digital cordless telephones. The device provides a p/4 shift QPSK modem function and a CODEC function which performs transcoding between the voice band analog signal and 32 kbps ADPCM data. The MSM7584C is ideal for use in a handset of the PHS (Personal Handyphone System).
FEATURES
(p/4 Shift QPSK Modem) * Built-in root Nyquist filter (a (rolloff rate) = 0.5) for the baseband limiter * Differential I and Q analog outputs * The DC offset and gain can be adjusted with respect to the differential I and Q analog outputs * Completely digitized p/4 shift QPSK demodulator system * Input IF signal frequency of 1.2 MHz or 10.8 MHz is available. * Built-in A/D converter for RSSI detection (ADPCM CODEC) * ADPCM : ITU-T Recommendations G.721 (32 kbps) * Transmit/receive full duplex capability * PCM interface code format: selectable between m-law and A-law * Built-in transmit/receive mute function and transmit/receive programmable gain setting function * Side tone path formation and level adjustment capabilities * Built-in DTMF tone and other tones * Built-in VOX function * Built-in speech recording/playing interface * Built-in 150 W driving OP AMP * Built-in various analog switches (Common) * Single 3V power supply (VDD: 2.7 V to 3.6 V) * Mode setting through serial interface * Low power consumption When the modem unit is operating : When the ADPCM CODEC unit is operating : When in the power down mode : * Package: 80-pin plastic TQFP (TQFP80-P-1212-0.50-K)
13 mA Typ. (VDD = 3.0 V) 7 mA Typ. (VDD = 3.0 V) 0.03 mA Typ. (VDD = 3.0 V) (Product name : MSM7584CTS-K)
1/57
Semiconductor
MSM7584C
BLOCK DIAGRAM
SL1 SL2
IFIN
Phase detector
IFSEL (From CR)
Delay detector
AFC
Judge
RXD RXC RXSC VDDM DGM AGM RPR AFC/RCW SLS
PDN0 PDN1 PDN2
D E C
SL1 SL2 DPLL S E L
I+ I- Q+ Q- DIN EXCK DEN DOUT RESET RO0 to RO1
+1
LPF
-1 +1
D/A ATT
DC adjust
Root Nyquist LPF 3.84M To D/A TXCSEL (From CR) To MODEM
S E L
S/P MAPPING PLL 384k 1/10 8b A/D Conv.
+ -
BSTO TXD TXW TXCI TXCO RSGAIN RSSI SGRS
LPF
-1
D/A ATT
DC adjust
Control register 2b To internal SG inside modem VREF
R
To CODEC
Offset adjust
SGM SGCR SGCT
T
Serial Register Controller Voice Detect
BPF
S E L
Receiver Transmitter
RC filter A/D converter
DIO WE SAD SAS TAS RWCK CS1 CS2 VOXO IS PCMSI PCMSO BCLK SYNC PCMRI PCMRO IR VOXI RXMUTE MLV2 MLV1 MLV0
AIN- AIN+ GSX PWI AOUT- AOUT+ VFRO SAO
- +
Compander ATT
ADPCM CODER
150 W driving AMP
- + Noise generator -1 +1 RC filter +1 SW1 VDD SW3 SW2 D/A converter
TONE generator
ATT
Power detect
P/S & S/P
LPF
+
+
ATT
SW4 SW5
S E L
Expander From CR
ADPCM DECODER
TOUT1 TOUT2 TOUT3
PDN3 VDDC DGC AGC
IO1 IO2
IO3
IO4
IO5
IO6
IO7
MCK
2/57
Semiconductor
MSM7584C
PIN CONFIGURATION (TOP VIEW)
RSGAIN
AOUT+
AOUT-
VDDM
SGCR
SGRS
SGCT
VFRO
RSSI
AIN+ 62
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
PDN0 PDN1 PDN2 PDN3 SLS AFC/RCW RPR RXC RXD RXSC BSTO TXW TXD TXCO TXCI IFIN DGM PCMRO PCMRI IR
61
AIN-
AGM
SGM
SAO
AGC
PWI
Q-
Q+
I-
I+
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41
GSX IO1 IO2 IO3 IO4 VDDC IO5 IO6 IO7 TOUT1 TOUT2 TOUT3 RO0 RO1 SAD WE SAS TAS RWCK DIO
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39 CS1
PCMSI
PCMSO
RXMUTE
VOXI
VOXO
SYNC
DGC
DIN
MLV2
MLV1
MLV0
RESET
DOUT
IS
BCLK
EXCK
MCK
DEN
80-Pin Plastic TQFP
CS2
40
3/57
Semiconductor
MSM7584C
PIN AND FUNCTIONAL DESCRIPTIONS
(ADPCM CODEC) AIN+, AIN-, GSX Transmit analog inputs and transmit level adjustment pin. The AIN- input is connected to the inverting input of the internal transmit amplifier and AIN+ input is connected to the non-inverting input. The GSX pin is connected to the output pin of the amplifier. See Figure 1 for level adjustment. VFRO, SAO Receive analog output and sounder output. VFRO is a receive filter output pin and SAO is a sounder output pin. These outputs can directly drive the load of over 10 kW. When the system is in the power down mode, these outputs become high impedance. AOUT+, AOUT-, PWI Input and outputs for internal operation amplifier. See Figure 1 for connection. When the system is in the power down mode, these outputs become high impedance. The AOUT- and AOUT+ outputs can directly drive the load of over 150 W.
4/57
Semiconductor
MSM7584C
AIN- Vi R1 C1 Differential analog input signal C1 Transmit gain : (VGSX2/Vi) = R2/R1 R1 R2 AIN+ R2 Reference voltage generator
- +
to ENCODER
GSX SGCT
SGCR
VFRO
+1
Receive side output signal Sounder output signal gain = R4/R3
SAO
-1
from DECODER SELECT
R3 R4 Sounder output signal
PWI
- +
150 W driving amplifier
AOUT- AOUT+
-1
Figure 1 Analog Interface
5/57
Semiconductor SGCT, SGCR
MSM7584C
Outputs for CODEC analog signal ground. The output voltage is approximately 1.4 V. Insert 10 mF and 0.1 mF bypass capacitors (ceramic type) between these pins and the AG pin. When the device is in power down mode, the output is 0 V. SGCT is used for transmitting and SGCR is for receiving. AGC ADPCM CODEC analog ground (0 V). DGC ADPCM CODEC digital ground (0 V). Since this pin is internally separated from AGC and AGM (modem ground pin), this pin must be connected to these pins as close as possible on the circuit board. VDDC ADPCM CODEC 3 V power supply. Connect this pin to the MODEM power Supply VDDM. PDN3 ADPCM CODEC power down control input. When this pin is set to "0" level, the device enters power down mode. During normal operation mode, set this pin to "1" level. The power down mode is controlled by CR0 - B5 of the control register ORed with the signal from the PDN3 pin. Therefore, when using this pin, set CR0 - B5 to digital "0".
6/57
Semiconductor PCMSO
MSM7584C
Transmit PCM data output. This PCM output signal is output from MSB synchronously with the rising edge of BCLK and XSYNC. PCMSI Transmit PCM data input. This signal is converted to the ADPCM data. The PCM signal is shifted in on the falling edge of BCLK. Normally, this pin is connected to PCMSO. PCMRO Receive PCM data output. The PCM signal is the output signal after ADPCM decoder processing. This signal is serially output from the MSB synchronously with the rising edge of BCLK and RSYNC. PCMRI Receive PCM data input. The PCM input signal is shifted in on the rising edge of BCLK input from MSB. Normally, this pin is connected to PCMRO. IS Transmit ADPCM signal output. This signal is the output signal after ADPCM encoding, and is serially output from MSB synchronously with the rising edge of BCLK and XSYNC. This pin is an open drain output which requires a pull-up resistor and goes to a high impedence state during power-down mode. IR Receive ADPCM signal input. Input data is shifted in serially from MSB on the rising edge of BCLK synchronously with RSYNC. BCLK Shift clock input for the PCM data (PCMSO, PCMSI, PCMRO, PCMRI) and the ADPCM data (IS, IR) . The frequency ranges from 64 kHz to 2048 kHz. SYNC 8 kHz synchronous signal input for transmit/receive PCM and ADPCM data. This signal should be synchronous with BCLK. SYNC is used for indicating MSB of the transmit serial PCM and ADPCM data stream.
7/57
Semiconductor RXMUTE
MSM7584C
Receive voice path mute control input. When this pin is at "0" level, the device enters normal mode. When at "1" level, the voice level is muted to the value which has been set by MLV2, MLV1, MLV0. This pin is internally ORed like CR1-B3. Therefore, when using this pin, set CR1-B3 to digital "0". MLV2, MLV1, MLV0 Receive voice path mute level setup signals. See the control register map for control method. These signals are internally ORed with CR1-B2, B1, B0, respectively. Therefore, when using this pin, set these register data to digital "0".
8/57
Semiconductor VOXO
MSM7584C
Transmit VOX function signal output. VOX function is used to recognize the presence or absence of the transmit voice signal by detecting the signal energy. "1" and "0" levels on this pin correspond to the presence and the absence, respectively. This result also appears at the register CR7 - B7. The signal energy detect threshold is set by the control register data CR6 - B6, B5. VOXI Signal input for receive VOX function. The "1" level on VOXI indicates the presence of voice signal, in which case the decoder block processes normal receive signal and the voice signal appears at analog output pins. The "0" level indicates the absence of voice signal, in which case the background noise generated in this device is transferred to the analog output pins. The background noise amplitude is set by the control register CR6. Because this signal is ORed with the register data CR6 - B3, the control register data CR6 - B3 should be set to digital "0".
Input voice signal GSX2 pin
VOXO pin
Voice
Silence
Voice
Voice detection time TVXON
Silence detection time (Hangover time) TVXOFF
(a) Transmission Side VOX Function Timing Diagram
VOXI pin
Voice
Silence
Voice
Regenerated voice VFRO pin
Regenerated voice signal generation time
Internal background noise generation time
(b) Receive Side VOX Function Timing Diagram
Note: The VOXO and VOXI pin function are enabled when CR6 - B7 is set to "1". Figure 2 VOX Function 9/57
Semiconductor
MSM7584C
(Voice Recording Serial Controller) DIO Input/output pin that outputs write data and to input read data. Connect this pin to the DIN pin, DOUT pin of the serial registers and the DOUT pin of the serial voice ROM. If neither a serial register nor a serial voice ROM is connected, pull this pin up with an approx. 50 kW resistor. WE Output that selects the read mode or write mode. Connect this pin to the WE pin of the serial registers. SAD Read/write start address output. Connect this pin to the SAD pin of the serial registers and the SADX pin of the serial voice ROM. SAS Output of clocks for writing serial address. Connect this pin to the SAS pin of the serial registers and the SASX and SASY pins of the serial voice ROM. TAS Strobe signal output that sets the serial address which is entered from the SAD pin, to the address counter inside the serial register/serial voice ROM. Connect this pin to the TAS pins of the serial registers and serial voice ROM. RWCK Output of clocks for reading data from or writing data to the serial registers. Connect this pin to the RWCK pin of the serial registers and the PDCK pin of the serial voice ROM. CS1, CS2 Chip select pins. Connect CS1 to the CS pin of the serial registers. Connect CS2 to the CS pin of the serial voice ROM.
10/57
Semiconductor
MSM7584C
(Modem) TXD 384 kbps transmit data input. TXCI Transmit clock input. When the control register CR14 - B6 is "0", a 384 kHz clock pulse synchronous with TXD should be input to this pin. This clock pulse should be continuous because this device use APLL to generate an internal clock pulse. When CR14 - B6 is "1", a 3.84 MHz clock pulse should be input to this pin. When the 3.84 MHz clock pulse is applied, a 384 kHz clock pulse, which is generated by dividing the TXCI by 10, is output to the TXCO pin. The transmit data, synchronous to the 384 kHz clock pulse, should be input to the TXD. In this case the devices do not use APLL, and the 3.84 MHz clock pulse need not be continuous. (Refer to Fig. 3) TXCO Transmit clock output. When CR14 - B6 is "0", TXCO outputs the 384 kHz clock pulse (APLL output) for monitoring purposes. When CR14 - B6 is "1", this pin outputs a 384 kHz clock pulse generated by dividing the TXCI input by 10. (Refer to Fig. 3) TXW Transmit data window signal input. The transmit timing signal for the burst data is input to this pin. If TXW is "1", the modulation data is output. (Refer to Fig. 3)
11/57
Semiconductor
MSM7584C
(1) CR14 - B6 = "0"
TXD TXCI (384kHz) TXW TXCO (384kHz) I, Q
D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 Dn-1 Dn
Delay of 6.25 symbols
BSTO
(2) CR14 - B6 = "1"
TXD TXCI (3.84MHz) TXW TXCO (384kHz) I, Q
D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13
Delay of 6.25 symbols
BSTO
,
Ramp rise-up 2 symbols Delay of 6.25 symbols Ramp Fall-down 2 symbols Dn-1 Dn Ramp rise-up 2 symbols Delay of 6.25 symbols Ramp Fall-down 2 symbols
Figure 3 Transmit Timing Diagram
12/57
Semiconductor BSTO
MSM7584C
BSTO is the modulator side burst output position specification signal. The burst time and position of the I and Q analog output including the lamp bits are output. (Refer to Fig. 3) I+, I- Quadrature modulation signal I Component differential analog output. Their output levels are 500 mVPP (maximum) with 1.6 Vdc as the center value. The output pin load conditions are: R 10 kW, C 20 pF. The gain of these pins can be adjusted using the control register CR15 - B7 to B4, and the offset voltage at the I- pin can be adjusted using CR16 - B7 to B3. Q+, Q- Quadrature modulation signal Q component differential analog outputs. Their output levels are 500 mVPP (maximum) with 1.6 Vdc as the center value. The output pin load conditions are: R 10 kW, C 20 pF. The gain of these pins can be adjusted using the control register CR15 - B7 to B4, and the offset voltage at the Q- pin can be adjusted by using CR17 - B7 to B3. SGM MODEM internal reference voltage output. The output voltage value is approximately 2.0 V. Insert a bypass capacitor of approximately 0.1 mF between this pin and the AGM pin.
13/57
Semiconductor PDN0, PDN1, PDN2
MSM7584C
Various power down controls. PDN0 controls the standby mode/communication mode; PDN1 controls the modulator; PDN2 controls the demodulator. Refer to Table 1 for details. Table 1 Description of Modem Power Down Control
PDN0 PDN2 PDN1 Standby Mode 0 0 Communication Mode 1 0/1 0/1 0 0 1 0 Operation State Entire system is powered down. The control register is not reset. Modulator unit is powered off. (VREF and PLL also powered off.) Demodulator unit is powered on. Modulator unit is powered off. (VREF and PLL are powered on.) I and Q outputs are in a high impedance state. Only the demodulator clock regenerator unit is powered on. 1 0 1 Modulator unit is powered off. (VREF and PLL are powered on.) I and Q outputs are in a high impedance state. Demodulator unit is powered on. 1 1 1 1 0 1 Modulator unit is powered on. Only the demodulator clock regenerator unit is powered on. Modulator unit is powered on. Demodulator unit is powered on. Mode F Mode E Mode D Mode C Mode Name Mode A Mode B
14/57
Semiconductor VDDM +3 V power supply for the modem unit. Connect this pin to the ADPCM CODEC power supply VDDC on the board. AGM Modem analog signal ground. DGM
MSM7584C
Modem digital signal ground. Since this pin is internaly separated from AGM, AGC, and DGC, this pin must be connected to theses pins on the board. MCK Master clock input. The clock frequency is 19.2 MHz. The master clock must always be input to the ADPCM CODEC and MODEM except the device being in power down mode because the both units share the master clock. If the input level is less than 2 V, the master clock must be input after DC-component is cut by an approx. 1000 pF capacitor. (See the application circuit example.) IFIN Modulated signal input for the demodulator unit. The CR14 - B4 can select an IF frequency of 1.2 MHz or 10.8 MHz. RXD, RXC, RXSC Receive data, receive clock (384 kHz), receive symbol clock (192 kHz) outputs. When the power is turned on, outputs in which a clock regeneration circuit selected by SLS appear on these output pin.
RXD RXC RXSC SLS
1 Symbol The regenerated data and clock are selected asynchronously by the SLS signal.
Figure 4 Timing Diagram of RXD, RXC, and RXSC SLS Receive side operation slot selection signal. This device has two clock regeneration circuits and two AFC data memory registers. If SLS is at "0" level, slot 1 is selected; if SLS is at "1" level, slot 2 is selected. RPR High-speed phase clock control signal input for the clock regeneration circuit. If this pin is at "1" level, the clock regeneration circuit enters the high-speed phase clock mode. When the phase difference is less than a defined value, the circuit shifts to the low-speed phase clock mode automatically. If this pin is at "0" level, the circuit is always in the low-speed phase clock mode. 15/57
Semiconductor AFC/RCW
MSM7584C
AFC operation and clock regeneration range specification signal input. As shown in Figure 5, AFC information is reset when AFC/RCW and RPR go to "1" level. The AFC operation starts after a certain time elapses. The average number of AFC operation times is small when RPR is at "1" level. The average number of AFC operation times is large when RPR is at "0" level. If AFC/RCW is at "0" level, DPLL will not adjust the phase.
(CASE1) AFC/RCW RPR
AFC information is reset. Averag number of AFC operation times is small. Average number of AFC operation times is large. AFC information is maintained.
(CASE2) AFC/RCW RPR
"0" The clock generation circuit starts with the previous AFC information. Average number of AFC operation times is large. AFC information is maintained.
Figure 5 AFC Control Timing Diagram
16/57
Semiconductor (Common) RESET
MSM7584C
Device reset input. The control registers CR0 to CR22 all are reset to the initial values by setting this pin to "0" level. R0, R1 Output ports for the control register CR21. The data written in CR21 - B0 and B1 are output on the R0 and R1 pins. These pins become high impedance when the device is reset. DEN, EXCK, DIN DOUT Serial control ports for the microcontroller interface. The device has 23 bytes of control registers. Data is written and read by the external CPU using these ports. DEN is an enable signal input, EXCK is a data shift clock signal input, DIN is an address/data input, and DOUT is a data output. The input/output timing is shown in Fig. 6.
DEN
, ,
EXCK DIN W
A4 A3 A2 A1 A0 B7 B6 B5 B4 B3 B2 B1 B0
(a) Write Data Timing
DEN
EXCK
DIN
R
A4 A3 A2 A1 A0
DOUT
High Impedance
B7 B6 B5 B4 B3 B2 B1 B0
(b) Read Data Timing
Figure 6 MCU Interface I/O Timing
The control register map is shown in Table 2. As shown in Fig. 6, data should be written or read in continuous pulses of the EXCK signal or in 16 bits. IO1 to IO7
Input/output for internal analog switches. See the control register map (CR22) and circuit configuration for connection information and control method. TOUT1, TOUT2, TOUT3
Sign bit outputs for the tone generator. The outputs are controlled by the control register CR22. See the control register map and circuit configuration for connection information and control method. 17/57
Semiconductor
MSM7584C
Table 2 Control Register Map
Address Register name A4 A3 A2 A1 A0 CR0 CR1 CR2 CR3 CR4 CR5 CR6 CR7 CR8 CR9 00 00 00 00 00 00 00 00 01 01 000 00 01 01 10 10 11 11 Data Description B7 A/m B6 -- B5 B4 B3 PDN RX RX MUTE RX GAIN3 Tone G3 TONE3 -- VOX IN -- ST4 ST12 SPY4 SP4 SP12 CH4 -- B2 SA,VF_ OUT MLV2 RX GAIN2 Tone G2 TONE2 -- RX_N SEL -- ST5 -- SPY5 SP5 -- -- -- Qch GAIN2 -- -- Local INV0 ADO2 -- -- TOUT3 CONT B1 SAO/ VFRO MLV1 RX GAIN1 Tone G1 TONE1 CMD1 N_ LV1 BUSY ST6 -- SPY6 SP6 -- ADRD -- Qch GAIN1 -- -- -- ADO1 RS PDN RO1 TOUT2 CONT B0 SA,VF_ PDN MLV0 RX GAIN0 Tone G0 TONE0 CMD0 N_ LV0 RPM ST7 -- SPY7 SP7 -- ADWT -- Qch GAIN0 -- -- -- ADO0 SEL RS RO0 RSSI A/D control General I/O MODEM control VOX play mode control ADPCM control Register function
PDN PDN ALL TX TX ON/ RX ON/ ADPCM TX 1 OFF OFF RST MUTE TX TX TX TX 0 GAIN3 GAIN2 GAIN1 GAIN0 S_ S_ S_ T ON/ 1 TONE2 TONE1 TONE0 OFF DTMF/ TONE_ 0 OT SEND TONE5 TONE4 SEND/ ROM/ 4M8M/ 1 -- REC SR 1M VOX ON ON OFF 0 ON/OFF LVL1 LVL0 TIME VOX Silence Silence 1 -- OUT L1 L0 ST0 ST8 SPY0 SP0 SP8 CH0 -- ST1 ST9 SPY1 SP1 SP9 CH1 TXC SEL Ich GAIN2 Ich Offset3 Qch Offset3 MODEM TEST2 ADO6 AD Offset3 -- SW2 CONT ST2 ST10 SPY2 SP2 SP10 CH2 MOD OFF Ich GAIN1 Ich Offset2 Qch Offset2 MODEM TEST1 ADO5 AD Offset2 -- SW3 CONT ST3 ST11 SPY3 SP3 SP11 CH3 IFSEL
000 001 010 011 100 101 110 111
CR10 0 1 CR11 0 1 CR12 0 1 CR13 0 1 CR14 0 1 CR15 0 1 CR16 1 0 CR17 1 0 CR18 1 0 CR19 1 0 CR20 1 0 CR21 1 0 CR22 1 0
Ich GAIN3 Ich 0 0 0 Offset4 Qch 0 0 1 Offset4 MODEM 0 1 0 TEST3 011 ADO7
Ich Qch GAIN0 GAIN3 Ich Ich Offset1 Offset0 Qch Qch Offset1 Offset0 MODEM Local TEST0 INV1 ADO4 AD Offset1 -- SW4/5 CONT ADO3 AD Offset0 -- AOUT PDN
AD 1 0 0 Offset4 101 110 -- SW1 CONT
TOUT1 Switches CONT control
18/57
Semiconductor (RSSI-ADC) RSSI, RSGAIN
MSM7584C
RSSI input and level adjustment. RSSI is connected to the inverting input pin of the internal amplifier. RSGAIN is connected to the output pin of the amplifier. Adjust the gain and DC so that the signal amplitude is between 0.7 V and 2.1 V on the RSGAIN pin. See Fig. 7 for connection. Gain: A = R2/R1 = 1.4/ (Vmax - Vmin) if R1 + R2 20 kW DC adjustment value : Vadj = A/(1+A) ((Vmax + Vmin) /2- 1.4) Set the register CR20 to the DC adjustment value nearest to Vadj. See the control register map (CR20) for setup values. SGRS Internal reference voltage output for the RSSI - ADC. The output voltage is 2.0 V. Insert an approx. 0.1 mF bypass capacitor between this pin and the AGM pin.
RSGAIN
RSSI signal R1 Gain = R2/R1
R2 RSSI
- +
ADC
Control register CR19:B7 to B0
DC ADJUST
Reference voltage generator
CR20:B7 to B3
Figure 7 RSSI-ADC Interface
SGRS
19/57
Semiconductor
MSM7584C
ABSOLUTE MAXIMUM RATINGS
Parameter Power Supply Voltage Analog Input Voltage Digital Input Voltage Operating Temperature Storage Temperature Symbol VDD VAIN VDIN Top TSTG Condition -- -- -- -- -- Rating -0.3 to +5 -0.3 to VDD + 0.3 -0.3 to VDD + 0.3 -25 to +70 -55 to +150 Unit V V V C C
RECOMMENDED OPERATING CONDITIONS
Parameter Power Supply Voltage Operating Temperature Range High Level Input Voltage Low Level Input Voltage Digital Input Rise Time Digital Input Fall Time Digital Output Load Bypass Capacitor for SG Bypass Capacitor for SG Master Clock Frequency Master Clock Duty Ratio Modulator Side Input
Modem Unit
(VDD = 2.7 V to 3.6 V, Ta = -25C to +70C) Min. 2.7 -25 0.45 VDD 0 -- -- 500 -- 10 + 0.1 0.1 -- 40 -- -- 40 45 Fig.10 -- -- 64 -- 40 100 100 Fig.8 1 BCLK 100 100 Typ. -- -- -- -- -- -- -- -- -- -- 19.2 50 384 3.84 50 50 -- -- -- 8.0 50 -- -- -- -- -- Max. 3.6 +70 VDD 0.16 VDD 50 50 -- 100 -- -- -- 60 -- -- 60 55 200 200 2048 -- 60 -- --
125ms-1BCLK
Symbol VDD Ta VIH VIL tIr tIf RDL CDL CSG1 CSG2
Conditon --
Unit V C V V ns ns W pF mF mF MHz % kHz MHz % % ns ns kHz kHz % ns ns ms ns ns
Input pins fully digital Input pins fully digital Input pins fully digital Input pins fully digital IS (Pull-up resistor) Input pins fully digital Between SGCT/R and AGC Between SGM, AGM and SGRS, AGM
FMCK MCK DMCK MCK FTXC1 FTXC2 DCIF TXCI (When CR14 - B6 = "0") TXCI (When CR14 - B6 = "1") IFIN
Frequency Clock Duty Ratio IF Input Duty Ratio Transmit Sync Pulse Setting Time Bit Clock Frequency Synchronous Signal Frequency Clock Duty Ratio
DCKM IFCK, TXCI, EXCK
tXSM, tSXM TXCITXW tDSM, tDHM TXCITXD
FBCK
BCLK
FSYNC XSYNC, RSYNC DCKC BCLK, EXCKC
CODEC Unit
Transmit Sync Pulse Setting Time tXSC, tSXC BCLKXSYNC
Receive Sync Pulse Setting Time tRSC, tSRC BCLKRSYNC tWSC XSYNC, RSYNC Synchronous Signal Width PCM, ADPCM Setup Time PCM, ADPCM Hold Time tDSC tDHC -- --
-- --
20/57
Semiconductor
MSM7584C
ELECTRICAL CHARACTERISTICS
DC Characteristics
Parameter Symbol IDD1 Power Supply Current (Modem) (When CODEC is in a Power Down State) IDD2 IDD3 IDD4 IDD5 IDD6 Power Supply Current (CODEC) (When Modem is in a Power Down State) Power Supply Current (RSSI-ADC) Input Leakage Current High Level Output Voltage Low Level Output Voltage Output Leakage Current Input Capacitance IDD7 IDD8 IDD9 IDD10 IIH IIL Condition Mode A (When VDD = 3.0 V) Mode B (When VDD = 3.0 V) Mode C (When VDD = 3.0 V) Mode D (When VDD = 3.0 V) Mode E (When VDD = 3.0 V) Mode F (When VDD = 3.0 V) When operating* (When no signal, and VDD = 3.0 V) When powered down (When VDD = 3.0 V) CR22-B3 = "1" (When VDD = 3.0 V) VI = VDD VI = 0 V (VDD = 2.7 V to 3.6 V, Ta = -25C to +70C) Min. -- -- -- -- -- -- -- -- -- -- -- -- 0.5 VDD 0.8 VDD 0 -- -- Typ. 0.03 4.5 4.5 10.5 8.5 13.0 7.0 11.0 0.03 2.0 -- -- -- -- 0.2 -- 5 Max. 0.1 10.0 10.0 22.0 18.0 27.0 15.0 18.0 0.1 4.0 2.0 0.5 VDD VDD 0.4 10 -- Unit mA mA mA mA mA mA mA mA mA mA mA mA V V V mA pF
VOH1 IOH = 0.4 mA VOH2 IOH = 1 mA VOL IO CIN IOL = -1.2 mA (IS pin is pulled up with 500 W resistor) IS pin --
*
IDD7 applies when CRC0 - B0 = "0" and CR22 - B3 = "0"; IDD8 applies when operating in other conditions.
21/57
Semiconductor Analog Interface Characteristics (RSSI - ADC)
MSM7584C
(VDD = 2.7 V to 3.6 V, Ta = -25C to +70C) Parameter Input Resistance Output Resistance Load Output Capacitance Load Input Voltage Range Offset Voltage Adjust Range Offset Voltage Adjust Accuracy A/D Conversion Resolution Symbol RINAD RSSI RLCAD RSGAIN CLAD RSGAIN VINAD When a RSGAIN signal is output. OVLAD OVSAD -- When offset voltage is adjusted per LSB step. Condition Min. 10 10 -- 0.7 -400 -12.5 -- Typ. -- -- -- -- -- -- 5.5 Max. -- -- -- 2.1 375 12.5 -- Unit MW kW pF V mV mV mV
RESAD One LSB step
Digital Interface Characteristics (RSSI - ADC)
Parameter Output Delay Time
Symbol
Condition Cload = 50 pF
(VDD Referrence Fig.12
= 2.7 V to 3.6 V, Ta = -25C to +70C) Min. -- Typ. 5 Max. -- Unit ms
tDAD
22/57
Semiconductor Analog Interface Characteristics (Modem)
Parameter Output Resistance Load Output Capacitance Load Output DC Voltage Level Output AC Voltage Level Output DC Voltage Adjustment Level Range Output AC Voltage Adjustment Level Range Out-of-band Spectrum Modulation Accuracy Demodulator Side IF Input Level IFIN Input Impedance SGM Output Voltage SGM Output Impedance MCK Input Level MCK Input Impedance Symbol RLIQ CLIQ Condition I+, I-, Q+, Q- I+, I-, Q+, Q- I+, I-, Q+, Q- (For TXD = 0 continuous input) -- --
MSM7584C
(VDD = 2.7 V to 3.6 V, Ta = -25C to +70C) Min. 10 -- 1.55 -- -- -- -- -- -- 0.5 -- -- -- 0.7 -- Typ. -- -- 1.6 360 45 4 -- -- 1.0 -- 20 2.0 1.5 -- 20 Max. -- 20 1.65 -- -- -- 60 65 3.0 VDD -- -- -- 2.0 -- Unit kW pF V mVPP mV % dB dB % rms VPP kW V kW VPP kW
VDCM I+, I-, Q+, Q- (TXW = 0) VACM DCVL ACVL
P600 600 kHz detuning P900 900 kHz detuning EVM IFV RIF VSGM RSGM IX RX -- IFIN input level DC impedance -- -- -- DC impedance
Digital Interface Characteristics (Modem)
(VDD = 2.7 V to 3.6 V, Ta = -25C to +70C) Parameter Transmit Digital I/O Setting Time Receive Digital I/O Setting Time Symbol Condition Reference Fig. 10 Fig. 11 Min. 0 0 0 Typ. -- -- -- Max. 200 400 200 Unit ns ns ns tXDM1,2 Cload = 50 pF tXDM3,4 tRDM1,2 Cload = 50 pF
23/57
Semiconductor Analog Interface Characteristics (CODEC)
MSM7584C
(VDD = 2.7 V to 3.6 V, Ta = -25C to +70C) Parameter Input Resistance Output Resistance Load Symbol RINC RLC1 RLC2 RLC3 CLC1 Output Capacitance Load CLC2 CLC3 VOC1 Output Voltage Level (*1) VOC2 VOC3 Offset Voltage SGCT, SGCR Output Voltage SGCT Output Impedance SGCR Output Impedance Analog Switch OFF Resistance Analog Switch ON Resistance GSX VFRO, SAO AOUT GSX VFRO, SAO AOUT GSX (RL = 20 kW) VFRO, SAO (RL = 10 kW) AOUT (RL = 150 W) Condition AIN+, AIN-, PWI Min. 10 20 10 150 -- -- -- -- -- -- -100 -20 -- -- -- 50 50 Typ. -- -- -- -- -- -- -- -- -- -- -- -- 1.4 40 4 -- 100 Max. -- -- -- -- 100 100 100 1.3 1.3 1.3 100 20 -- 80 8 -- 200 Unit MW kW kW W pF pF pF VPP VPP VPP mV mV V kW kW MW W
VOFC1 VFRO, SAO VOFC2 GSX, AOUT VSGC SGCT, SGCR RSGCT SGCT RSGCR SGCR RSWof SW1 to SW5 RSWon SW1 to SW5
*1 -7.7 dBm (600 W) = 0 dBm0, +3.14 dBm0 = 1.30 VPP
24/57
Semiconductor Digital Interface Characteristics (CODEC)
MSM7584C
(VDD = 2.7 V to 3.6 V, Ta = -25C to +70C) Parameter Digital Output Delay Time PCM, ADPCM Interface Symbol tSDXC, tSDRC tXDC1, tRDC1 tXDC2, tRDC2 tXDC3, tRDC3 tC1 tC2 tC3 tC4 tC5 Serial Port Digital I/O Timing Characteristics tC6 tC7 tC8 tC9 tC10 tC11 tC12 EXCK Clock Frequency Fexck EXCK -- Cload = 50 pF Fig. 9 Condition Reference Min. 0 0 0 0 50 50 50 50 100 50 50 0 50 50 0 200 -- Typ. -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Max. 200 (100) 200 (100) 200 (100) 200 (100) -- -- -- -- -- -- -- 100 -- -- 50 -- 10 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns MHz Cload = 50 pF pull-up resistor: 500 W Fig. 8 Items in parenthesis mean Cload = 10 pF, and the pull-up resistor 2 kW
25/57
Semiconductor Serial Interface Characteristics
Parameter Control Register Data Input BUSY Bit RPM Bit
Symbol
MSM7584C
Condition Reset Rising Active time Rising Falling at Stop command
(VDD Referrence
= 2.7 V to 3.6 V, Ta = -25C to +70C) Min. -- -- -- -- -- -- Typ. -- -- -- -- -- -- Max. 200 200 10 450 10 135 Unit ns ns ms ms ms ms
tCRW Write tCRR tBSR tBSH tRPR tRPF
Fig.15
26/57
Semiconductor AC Characteristics (CODEC)
MSM7584C
(VDD = 2.7 V to 3.6 V, Ta = -25C to +70C) Parameter Symbol LOSS T1 LOSS T2 Transmit Frequency Response LOSS T3 LOSS T4 LOSS T5 LOSS T6 LOSS R1 Receive Frequency Response LOSS R2 LOSS R3 LOSS R4 LOSS R5 SD T1 Transmit Signal to Distortion Ratio (*1) SD T2 SD T3 SD T4 SD T5 SD R1 Receive Signal to Distortion Ratio (*1) SD R2 SD R3 SD R4 SD R5 GT T1 Transmit Gain Tracking GT T2 GT T3 GT T4 GT T5 GT R1 Receive Gain Tracking GT R2 GT R3 GT R4 GT R5 1020 1020 1020 1020 Condition Frequency (Hz) 0 to 60 300 to 3 k 1020 3300 3400 3968.75 0 to 3000 1020 3300 3400 3968.75 3 0 -30 -40 -45 3 0 -30 -40 -45 3 -10 -40 -50 -55 3 -10 -40 -50 -55 -0.2 -0.5 -1.2 -0.2 -0.5 -1.2 -0.2 0 -0.15 0 13 35 35 35 28 23 35 35 35 28 23 -0.2 0 Level dBm0 Min. 25 -0.15 -0.15 0 13 -0.15 Typ. -- -- Reference -- -- -- -- Reference -- -- -- -- -- -- -- -- -- -- -- -- -- -- Reference -- -- -- -- Reference -- -- -- 0.2 0.5 1.2 0.2 0.5 1.2 0.2 0.80 0.80 -- -- -- -- -- -- -- -- -- -- -- 0.2 0.80 0.80 -- 0.20 Max. -- 0.20 Unit dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB
*1 P-message filter used
27/57
Semiconductor AC Characteristics (CODEC) (Continued)
Parameter Symbol NIDLT NIDLR AVT AVR PSRRR Condition Frequency (Hz) -- -- 1020 Level dBm0 AIN = SG (*2) 0 Noise level: 50 mVPP Other -- -- GSX2 VFRO --
MSM7584C
(VDD = 2.7 V to 3.6 V, Ta = -25C to +70C) Min. -- -- 0.285 0.285 30 30 Typ. -- -- 0.320 0.320 -- -- Max. -68 (-75.7) -72 (-79.7) 0.359 0.359 -- -- Vrms Vrms dB dB dBm0p (dBmp) Unit
Idle Channel Noise (*1)
Absolute Level (*3) Power Supply Noise Rejection Ratio
PSRRT Noise frequency: 0 kHz to 50 kHz
*1 P-message filter used *2 PCMRI input: "11010101" (A-law), "11111111" (m-law) *3 0.320 Vrms = 0 dBm0 = -7.7 dBm (600 W) ADPCM characteristics are fully compliant with ITU-T Recommendation G.721. AC Characteristics (DTMF and Other Tones)
Parameter Frequency Deviation Tone Reference Output Level (*1) Symbol DFT1 DFT2 VTL VTH VRL VRH DTMF tones Other various tones Transmit side tone Receive side tone VTH/VTL, VRH/VRL DTMF (low group) DTMF (high group), other DTMF (low group) DTMF (high group), other Condition (VDD = 2.7 V to 3.6 V, Ta = -25C to +70C) Min. -7 -7 -18 -16 -4 -2 1 Typ. -- -- -16 -14 -2 0 2 Max. 7 7 -14 -12 0 2 3 Unit Hz Hz dBm0 dBm0 dBm0 dBm0 dB
DTMF Tone Level Relative Value RDTMF
*1 Not including programmable gain set values AC Characteristics (Gain Settings)
(VDD = 2.7 V to 3.6 V, Ta = -25C to +70C) Parameter Transmit/Receive Gain Setting Accuracy Symbol DG Condition For all gain set values Min. -1 Typ. 0 Max. 1 Unit dB
AC Characteristics (VOX Function)
(VDD = 2.7 V to 3.6 V, Ta = -25C to +70C) Parameter Transmit VOX Detection Time (Voice and Silence Detection Time) Transmit VOX Detection Level Accuracy (Voice Detection Level) DVX Symbol TVXON TVXOF Condition SilenceAEvoice VOXO pin: See Fig. 2 VoiceAEsilence Voice/silence differential: 10 dB Min. -- Typ. 5 Max. -- Unit ms ms
140/300 160/320 180/340
For detection level set values by CR6 - B6, B5
-2.5
0
2.5
dB
28/57
Semiconductor
MSM7584C
TIMING DIAGRAM
(ADPCM CODEC) Transmit Side PCM, ADPCM Timing
BCLK SYNC PCMSO tSDXC BCLK SYNC IS tSDXC 0 tXSC 1 tSXC tXDC1 2 3 4 5 6 7 8 9 10 0 tXSC 1 tSXC tXDC1 MSB 2 tWSC tXDC2 3 4 5 6 7 8 9 10
tXDC3 LSB
tXDC2
MSB
tXDC3 LSB
Receive Side PCM, ADPCM Timing
BCLK SYNC tDSC IR BCLK SYNC tRDC1 PCMRO tSDXC tRDC2 MSB tRDC3 LSB MSB 0 tRSC 1 tSRC 2 3 tDHC LSB 4 5 6 7 8 9 10 0 tRSC 1 tSRC 2 3 tWSC 4 5 6 7 8 9 10
Figure 8 PCM, ADPCM Interface Serial Port Timing for Microcontroller Interface
DEN tC2 EXCK tC1 1 tC3 2 3 tC6 4 tC7 tC5 5 6 7 13 14 15 16 tC9 tC10
tC4 W/R A4
DIN
A3
A2
A1
A0
B7 tC8
B1
B0
DOUT
B7
B1
B0
Figure 9 Serial Control Port Interface 29/57
Semiconductor
TIMING DIAGRAM
(Modem) Transmit Data Input Timing
TXCI [TXCO*] (384 kHz) TXW TXD 1
Transmit Clock (TXCO) Output Timing (When CR14 - B6 = 1)
TXCI (3.84 MHz) TXCO (384 kHz) 1 2 3 4 5 6 7
Transmit Burst Position (BSTO) Output Timing (When CR14 - B6 = 0)
TXCI (384 kHz) TXW 1 2 8 9 N N+1
, ,
MSM7584C
2 3 N-2 N-1 N N+1
tXSM
tXSM
tDSM tDHM
1
2
3
N-2
N-1
N
*TXCO in brackets [ ] is when CR14 - B6 = 1
8
9
10
tXDM1
tXDM2
tXDM1
N+17
N+18
N+19
tXDM3
BSTO
tXDM4
Figure 10 Modem Transmit Side (Modulator Side) Digital I/O Timing Receive Side Data I/O Timing
SLS
tRMS1
RCW
tRMS2 tRMS4
tRMS3
AFC
tRWM
RPR RXC
tRDM1
RXD
tRDM2
Figure 11 Receive Side (Demodulator Side) Digital I/O Timing
30/57
Semiconductor
MSM7584C
TIMING DIAGRAM
(RSSI - ADC) RSSI - ADC Output Timing
RSSI input (RSSIGAIN Pin) DEN
1
2
3
4
5
6
7
8
9
10
11
12
13
14
EXCK
1 1 0 0 1 1
DIN
R address = 10011
DOUT
Internal AD conversion output latch signal
AD conversion output delay time tDAD
Notes:
1. AD conversion output data corresponds to the RSSI analog input value between the rising edge of the 6th EXCK clock pulse and the start point of the AD conversion output delay time (tDAD). 2. Normal AD conversion output data is output approximately 1ms after the power down mode is cancelled. Figure 12 RSSI - ADC Output Timing

MSB
LSB AD conversion output data (8 bit)
31/57
Semiconductor
MSM7584C
TIMING DIAGRAM
(Serial Register Interface) Address Write/Read Timing
DEN
EXCK DIN (CR13) CR13 - (B1, B0) tCRW BUSY Serial register I/F tBSR Address data transfer tBSH X X
(ADWT, ADRD) (X, X) tCRR (0, 0)
Recording/Playback Timing
DEN
EXCK DIN (CR5) CR5 - (B1, B0) tCRW RPM Serial register I/F tRPR Recording/playback data transfer tRPF X X "1" "1"
(PLAY/REC) (X, X)
(STOP) (0, 0) tCRR
Figure 13 Serial Register Interface
32/57
Semiconductor Mode State Transition Time in Modem
MSM7584C
Note: Values not indicated are less than 1 ms.
1 ms Mode A Mode B PDN2 = 0 PDN2 = 1
Standby mode (PDN0 = 0) Communication mode (PDN0 = 1) 40 ms Mode E PDN1 = 1 PDN2 = 0 5 ms
5 ms
5 ms Mode C PDN1 = 0 PDN2 = 0 40 ms Mode F PDN1 = 1 PDN2 = 1 Mode D PDN1 = 0 PDN2 = 1
Figure 14 Transition Between Power-Down Mode and Power-ON Mode
33/57
Semiconductor Timing Diagram for Demodulator Control in Modem (Example)
1st slot R1 2nd slot R2 3rd slot R3
MSM7584C
Demodulator unit Modulator input data PDN2 SLS AFC/RCW RXD RXC
G
G
G
G
4th slot R4
G
"0"
(1) Control ch/ synchronous burst (SS + PR =64 bits)
240 bits 625ms 64 bits
RXD
G
G
G
G
G
G
G
G
R
R
R
R SS SS PR PR
PR UW
CR CR G
G
G
G
G
G
G
G
AFC/RCW RPR
56 bits
(2) When synchronization is not yet established AFC/RCW RPR
In the case of a personal station, drive RPR high in the initial state and wait for a control signal to come from the central station. Then, after a UW is detected, drive RPR low.
(3) Communication ch (SS + PR = 8 bits) RXD
G G G G G G G G R R R
8 bits R SS SS PR PR PR UW CR CR G G G G G G G G
AFC/RCW RPR
"0"
When the strength of the received wave is large When the strength of the received wave is small
Less than 30 bits
G : Guard bit R : Ramp bit SS : Start symbol bit RR : Preamble bit UM : Unique word bit CR : CRC bit
Figure 15 Modem Unit Demodulator Timing Diagram Example
34/57
Semiconductor FUNCTIONAL DESCRIPTION Control Register Description Table (ADPCM CODEC) (1) CR0 (Basic Operation Mode Settings)
B7 CR0 Initial Value (*) A/m SEL 0 B6 -- 0 B5 PDN ALL 0 B4 PDN TX 0 B3 PDN RX 0 B2 SA, VF _ OUT 0 B1
MSM7584C
B0 SA, VF _ PDN 0
SAO/VFRO 0
*
The initial value means a value which is set when the device is reset using the RESET signal.
B7: .............. PCM interface companding selection 0: m-law 1: A-law B6: .............. Not used B5: .............. Power down (entire unit) 0: Power ON 1: Power down ORed with the inverting external power down signal PDN3. When using this data, set PDN3 to "1". B4: .............. Power down (transmit side only) 0: Power ON 1: Power down B3: .............. Power down (receive side only) 0: Power ON 1: Power down B2: .............. Output from VFRO and SAO at a time 0: Receive side output signals are output from a pin selected by B1. 1: Receive side output signals are output from VFRO and SAO at a time. B1: .............. Receive side output switch control 0: Receive side output signals appear on the SAO (Sounder Amplifier Output) pin. 1: These signals appear on the VFRO (Receiver Amplifier Output) pin. B0: .............. Power down control for sounder output amplifier (SAO) and receiver output amplifier (VFRO). 0: When SAO is selected by CR0 - B1, VFRO is powered down. When VFRO is selected, SAO is powered down. 1: Both SAO and VFRO are powered ON.
35/57
Semiconductor
MSM7584C
(2) CR1 (ADPCM Operation Mode Settings)
B7 CR1 Initial Value TX ON/OFF 0 B6 RX ON/OFF 0 B5 ADPCM RESET 0 B4 TX MUTE 0 B3 RX MUTE 0 B2 MLV2 0 B1 MLV1 0 B0 MLV0 0
B7: .............. Transmit side PCM signal ON/OFF. 0: ON 1: OFF OFF: PCM idle pattern is transmitted. B6: .............. Receive side PCM signal ON/OFF. 0: ON 1: OFF OFF: PCM idle pattern is transmitted. B5: .............. ADPCM reset (as specified by G. 721) 1: reset B4: .............. Transmit side MUTE. 0: Transmit MUTE OFF. 1: Transmit MUTE ON. Transmit output is in an idle state. B3: .............. Receive side MUTE. This bit is ORed with the external control pin RXMUTE. 0: Receive side MUTE OFF. 1: Receive side MUTE ON. The receive side output signals are attenuated by the values represented by a combination of bits B2, B1, and B0 of the CR1. (For voice path only.) B2, B1, B0: An attenuation value is selected at receive side MUTE (CR1 - B3 = "1") (see Table 3). These bits are ORed with the external pins MLV2, MLV1, and MLV0. Table 3 MUTE Level Settings
B2 0 0 0 0 1 1 1 1 B1 0 0 1 1 0 0 1 1 B0 0 1 0 1 0 1 0 1 Attenuation value 0dB loss - 6dB loss -12dB loss -18dB loss -24dB loss -30dB loss -36dB loss MUTE (idle state)
36/57
Semiconductor
MSM7584C
(3) CR2 (PCMCODEC Operation Mode Settings and Transmit/Receive Gain Adjustment)
B7 CR2 Initial Value TX GAIN3 0 B6 TX GAIN2 0 B5 TX GAIN1 0 B4 TX GAIN0 0 B3 RX GAIN3 0 B2 RX GAIN2 0 B1 RX GAIN1 0 B0 RX GAIN0 0
B7, B6, B5, B4: ....... Transmit side signal gain adjustment (see Table 4) B3, B2, B1, B0: ....... Receive side signal gain adjustment (see Table 4) Table 4 Receive/Transmit Gain Settings
Transmit/ receive gain -16dB -14dB -12dB -10dB - 8dB - 6dB - 4dB - 2dB 0dB 2dB 4dB 6dB 8dB 10dB 12dB 14dB B7 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 B6 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 B5 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 B4 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 B3 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 B2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 B1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 B0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
The above gain settings table shows the transmit/receive voice signal gain settings and the transmit side gain settings for DTMF tones and other tones. Tone signal transmission is enabled by CR4 - B6 (discussed later), and the gain setting is set to the levels shown below. DTMF tones (low group): ................................. -16 dBm0 DTMF tones (high group) and other tones: ... -14 dBm0 For example, if the transmit gain set value is set to +8 dB (B7, B6, B5, B4) = (0, 1, 0, 0), then the following tones appear at the PCMSO pin. DTMF tones (low group): ................................. -8 dBm0 DTMF tones (high group) and other tones: ... -6 dBm0 -3 dBm0 (mixed tone) However, the gain of the receive side tone and the gain of the side tones (path from transmit side to receive side) are set by the CR3 register.
37/57
Semiconductor (4) CR3 (Side Tone and Tone Generator Gain Adjustment)
B7 CR3 Initial Value GAIN2 0 B6 GAIN1 0 B5 GAIN0 0 B4 TONE ON/OFF 0 B3 TONE GAIN3 0 B2 TONE GAIN2 0 B1
MSM7584C
B0 TONE GAIN0 0
Side Tone Side Tone Side Tone
TONE GAIN1 0
B7, B6, B5: ........ Side tone gain adjustment (refer to Table 5) B4: ..................... Tone generator ON/OFF 0: OFF 1: ON B3, B2, B1, B0: . Tone generator Receive side gain adjustment (refer to Table 6) Table 5 Side Tone Gain Settings
B7 0 0 0 0 1 1 1 1 B6 0 0 1 1 0 0 1 1 B5 0 1 0 1 0 1 0 1 Side Tone Gain OFF -15 dB -13 dB -11 dB -9 dB -7 dB -5 dB -3 dB
Table 6 Receive Side Tone Generator Gain Settings
B3 0 0 0 0 0 0 0 0 B2 0 0 0 0 1 1 1 1 B1 0 0 1 1 0 0 1 1 B0 0 1 0 1 0 1 0 1 Tone Generator Gain -32 dB -30 dB -28 dB -26 dB -24 dB -22 dB -20 dB -18 dB B3 1 1 1 1 1 1 1 1 B2 0 0 0 0 1 1 1 1 B1 0 0 1 1 0 0 1 1 B0 0 1 0 1 0 1 0 1 Tone Generator Gain -16 dB -14 dB -12 dB -10 dB -8 dB -6 dB -4 dB -2 dB
The receive side tone generator gain settings shown in Table 6 are set with the following levels as a reference. DTMF tones (low group): ................................. -2 dBm0 DTMF tones (high group) and other tones: ... 0 dBm0 For example, if the tone generator gain set value is set to -6 dB (B3, B2, B1, B0)=(1, 1, 0, 1), then tones at the following levels appear at the SAO+/SAO- or VFRO pin. DTMF tones (low group): ................................. -8 dBm0 DTMF tones (high group) and other tones: ... -6 dBm0 -3 dBm0 (mixed tone)
38/57
Semiconductor (5) CR4 (Tone Generator Operation Mode and Frequency Settings)
B7 CR4 Initial Value DTMF/ OTHERS SEL 0 B6 TONE SEND 0 B5 TONE5 0 B4 TONE4 0 B3 TONE3 0 B2 TONE2 0 B1
MSM7584C
B0 TONE0 0
TONE1 0
B7: ........................... Selection of DTMF signal and other tones (S tone, F tone, R tone, etc.) 0: Other tones 1: DTMF signal B6: ........................... Transmission side tone transmit 0: Voice signal transmit 1: Tone transmit B5, B4, B3, B2, B1, B0: Tone frequency setting (refer to Table 7) Table 7 Tone Generator Frequency Settings (a) When B7 = 1 (DTMF Tones)
B5 * * * * * * * * B4 * * * * * * * * B3 0 0 0 0 0 0 0 0 B2 0 0 0 0 1 1 1 1 B1 0 0 1 1 0 0 1 1 B0 0 1 0 1 0 1 0 1 Description 697 Hz + 1209 Hz 697 Hz + 1336 Hz 697 Hz + 1477 Hz 697 Hz + 1633 Hz 770 Hz + 1209 Hz 770 Hz + 1336 Hz 770 Hz + 1477 Hz 770 Hz + 1633 Hz B5 * * * * * * * * B4 * * * * * * * * B3 0 0 0 0 0 0 0 0 B2 0 0 0 0 1 1 1 1 B1 0 0 1 1 0 0 1 1 B0 0 1 0 1 0 1 0 1 Description 852 Hz + 1209 Hz 852 Hz + 1336 Hz 852 Hz + 1477 Hz 852 Hz + 1633 Hz 941 Hz + 1209 Hz 941 Hz + 1336 Hz 941 Hz + 1477 Hz 941 Hz + 1633 Hz
39/57
Semiconductor
MSM7584C
(b) When B7 = 0 (Other than DTMF Tones)
B5 B4 B3 B2 B1 B0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 Description 8 Hz Wamble 8 Hz Wamble 16 Hz Wamble 16 Hz Wamble 16 Hz Wamble 16 Hz Wamble 16 Hz Wamble 16 Hz Wamble 16 Hz Wamble 8 Hz Wamble B5 B4 B3 B2 B1 B0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 Description Single tone Single tone Single tone Single tone Single tone Single tone Single tone Single tone Single tone Single tone Single tone Single tone Single tone Single tone Single tone Single tone Single tone Single tone Single tone Single tone Single tone Single tone Single tone Single tone Single tone Single tone Single tone Single tone Single tone Single tone Single tone Single tone 0 400/500 Hz 1 800/1 Hz 0 400/500 Hz 1 400/1 Hz 0 667/800 Hz 1 800/1 Hz 0 1 k/1.33 kHz 1 2.7 k/1 kHz 0 2 k/2.1 kHz 1 2 k/2.7 kHz 0 1100 Hz 1 1142 Hz 0 1200 Hz 1 1210 Hz 0 1250 Hz 1 1300 Hz 0 1333 Hz 1 1360 Hz 0 1410 Hz 1 1455 Hz 0 1477 Hz 1 1500 Hz 0 3310 Hz 1 1600 Hz 0 1635 Hz 1 1710 Hz 0 1800 Hz 1 1900 Hz 0 2000 Hz 1 2100 Hz 0 2200 Hz 1 2285 Hz 0 2400 Hz 1 2500 Hz 0 2600 Hz 1 2670 Hz 0 2700 Hz 1 2820 Hz 0 2910 Hz 1 3000 Hz 0 3110 Hz 1 3200 Hz
0 2.6 k/2.7 kHz 16 Hz Wamble 1 3.2 k/3.31 kHz 16 Hz Wamble 0 400 kHz 1 2 kHz 0 2.7 kHz 1 400 kHz 0 350 + 440 kHz 1 400 + 480 kHz 0 480 + 620 kHz 1 350 kHz 0 400 kHz 1 440 kHz 0 480 kHz 1 500 kHz 0 533 kHz 1 571 kHz 0 620 kHz 1 667 kHz 0 727 kHz 1 800 kHz 0 888 kHz 1 1000 kHz 16 Hz Wamble 16 Hz Wamble 16 Hz Wamble 10 Hz Wamble Mixed tone Mixed tone Mixed tone Single tone Single tone Single tone Single tone Single tone Single tone Single tone Single tone Single tone Single tone Single tone Single tone Single tone
40/57
Semiconductor
MSM7584C
(6) CR5 (Control of Serial Register I/F)
B7 CR5 Initial Value SEND/ REC 0 B6 ROM/ SR 0 B5 4M8M/ 1M 0 B4 -- 0 B3 -- 0 B2 -- 0 B1 CMD1 0 B0 CMD0 0
B7: .............. Register I/F connection. 0: Connection with ADPCM receiver 1: Connection with ADPCM transmitter B6: .............. Switching between voice ROM and serial register. 0: Serial register 1: Voice ROM B5: .............. Capacitance of serial register to be connected. 0: 1 Mbit (MSM6389) 1: 4 Mbit (MSM6684), 8 Mbit (MSM6685) B1, B0: .......Serial register I/F command (CMD1, CMD0) = (0. 0): NOP (0. 1): PLAY (1. 0): REC (RECORD) (1. 1): STOP Note: CMD1 and CMD0 are reset to "0" after the instruction is executed. The PLAY and REC instructions must not be executed when BUSY (CR5 - B1) and RPM (CR5 - B0) are set to "1".
41/57
Semiconductor (7) CR6 (VOX Function Control)
B7 CR6 Initial Value VOX ON/OFF 0 B6 ON LVL1 0 B5 ON LVL0 0 B4 OFF TIME 0 B3 VOX IN 0 B2 LEVEL SEL 0 B1
MSM7584C
B0 LVL0 0
RX NOISE RX NOISE RX NOISE LVL1 0
B7: .............. VOX function ON/OFF 0: OFF 1: ON B6, B5: .......Transmit side voice/silence detector level settings (0,0): -20 dBm0 (0,1): -25 dBm0 (1,0): -30 dBm0 (1,1): -35 dBm0 B4: .............. Hangover time (refer to Fig. 2) settings 0: 160 ms 1: 320 ms B3: .............. Receive side VOX input signal 0: Internal background noise transmit 1: Voice receive signal transmit When using this data, set the VOXI pin to "0". B2: .............. Receive side background noise level setting 0: Internal automatic setting 1: Externa setting (by B1, B0) Internal automatic setting AE Sets to the voice signal level when B3 (VOXI) changes from "1" to "0". B1, B0: .......External setting background noise level (0,0): No noise (0,1): -45 dBm0 (1,0): -35 dBm0 (1,1): -25 dBm0
(8) CR7 (Detect Register: Read-only)
B7 CR7 Initial Value VOX OUT 0 B6 1 0 B5 0 0 B4 -- 0 B3 -- 0 B2 -- 0 B1 BUSY 0 B0 RPM 0 Silent Level Silent Level
B7: ........................... Transmit side voice/silence detection 0: Silence 1: Voice B6, B5: .................... Transmit side silence level (indicator) (0,0):Below -60 dBm0 (0,1): -50 to -60 dBm0 (1,0): -40 to -50 dBm0 (1,1): Above -40 dBm0 Note: These outputs are enabled when the VOX function is turned ON by CR6 - B7. B4 - B2: ................... Not used B1: ........................... Serial register I/F monitoring. This bit monitors the Read and Write of addresses at the serial register I/F. 0: Stop 1: Reading or Writing B0: ........................... Monitors serial register recording and playback. 0: Stop 1: Recording or Playing back
42/57
Semiconductor (9) CR8 (Start X-address 0 to 7)
B7 CR8 Initial Value ST0 0 B6 ST1 0 B5 ST2 0 B4 ST3 0 B3 ST4 0 B2 ST5 0 B1 ST6 0
MSM7584C
B0 ST7 0
CR9 (Start X-address 8 to 12)
B7 CR9 Initial Value ST8 0 B6 ST9 0 B5 ST10 0 B4 ST11 0 B3 ST12 0 B2 -- 0 B1 -- 0 B0 -- 0
CR8 (B7 to B0), CR9 (B7 to B3) : Recording/playback start X-address storage register (10) CR10 (Start Y-address 0 to 7)
B7 CR10 Initial Value SPY0 0 B6 SPY1 0 B5 SPY2 0 B4 SPY3 0 B3 SPY4 0 B2 SPY5 0 B1 SPY6 0 B0 SPY7 0
CR10 (B7 to B0) : Recording/playback stop Y-address storage register (11) CR11 (Stop X-address 0 to 7)
B7 CR11 Initial Value SP0 0 B6 SP1 0 B5 SP2 0 B4 SP3 0 B3 SP4 0 B2 SP5 0 B1 SP6 0 B0 SP7 0
CR12 (Stop X-address 8 to 12)
B7 CR12 Initial Value SP8 0 B6 SP9 0 B5 SP10 0 B4 SP11 0 B3 SP12 0 B2 -- 0 B1 -- 0 B0 -- 0
CR11 (B7 to B0), CR12 (B7 to B3) : Recording/playback stop X-address storage register
43/57
Semiconductor
MSM7584C
(12) CR13 (Channel Selection)
B7 CR13 Initial Value CH0 0 B6 CH1 0 B5 CH2 0 B4 CH3 0 B3 CH4 0 B2 -- 0 B1 ADRD 0 B0 ADWT 0
B7 - B3: ................... Channel selection (all 32 channels are selected by HEX code) B2: ........................... Not used B1: ........................... Address Read instruction 0: NOP 1: When "1" is written in this bit, the start/stop addresses corresponding to the channels specified by B7 - B3 are transferred from the channel index area of the serial register to CR8 - CR12. These bits are reset to "0"s after the addresses are transferred. B0: ........................... Address write instruction 0: NOP 1: When "1" is written in this bit, the start/stop address corresponding to the channel specified by B7 - B3 is transfered from CR8 - 12 to the channel index area of the serial register. These bits are reset to "0"s after the addresses are transferred. Note: When BUSY (CR7 - B1) and RPM (CR7 - B0) are set to "1", writing to ADRD and ADWT is not allowed.
44/57
Semiconductor (Modem) (13) CR14 (Basic Operation Mode Setting)
B7 CR14 Initial Value -- 0 B6 TXC SEL 0 B5 MOD OFF 0 B4 IFSEL 0 B3 -- 0 B2 -- 0 B1
MSM7584C
B0 TEST0 0
TEST1 0
B7, B3, B2: ........ Not used B6: ..................... Transmission timing clock selection 0: TXCI input: 384 kHz TXCO output: APLL 384 kHz output Transmit data TXD is input synchronously with the rising edge of TXCI. APLL is ON. 1: TXCI input: 3.84 MHz TXCO output: 384 kHz (TXCI divided by 10) Transmit data TXD is input synchronously with the rising edge of TXCO. APLL is OFF. B5: ..................... Modulation OFF/ON control 0: Modulation ON 1: Modulation OFF (fixed phase) B4: ..................... Receive side input IF frequency selection 0: 1.2 MHz 1: 10.8 MHz B1, B0: .............. Device test control bits These bits should be set to "0" for normal use.
45/57
Semiconductor (14) CR15 (I and Q Gain Adjustment)
B7 CR15 Initial Value lch GAIN3 0 B6 lch GAIN2 0 B5 lch GAIN1 0 B4 lch GAIN0 0 B3 Qch GAIN3 0 B2 Qch GAIN2 0 B1 Qch
MSM7584C
B0 RX Qch GAIN0 0
GAIN1 0
B7 - B4: ......I+ and I- output gain setting: 3 mV steps (refer to Table 8) B3 - B0: ......Q+ and Q- output gain setting: 3 mV steps (refer to Table 8) Table 8 I and Q Channel Amplitude Value
CR1 - B7 CR1 - B3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 B6 B2 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 B5 B1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 B4 B0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 Description Amplitude Value : 1.042 (Reference Value) 1.036 1.030 1.024 1.018 1.012 1.006 1.000 (Reference Value) 0.994 0.988 0.982 0.976 0.970 0.964 0.958 0.952
46/57
Semiconductor (15) CR16 (I- Output Offset Voltage Adjustment)
B7 CR16 Initial Value lch Offset4 0 B6 lch Offset3 0 B5 lch Offset2 0 B4 lch Offset1 0 B3 lch Offset0 0 B2 -- 0 B1 -- 0
MSM7584C
B0 -- 0
B7 - B3: ......I- output pin offset voltage adjustment (refer to Table 9) B2 - B0: ......Not used (16) CR17 (Q- Output Offset Voltage Adjustment)
B7 CR17 Initial Value Qch Offset4 0 B6 Qch Offset3 0 B5 Qch Offset2 0 B4 Qch Offset1 0 B3 Qch Offset0 0 B2 -- 0 B1 -- 0 B0 -- 0
B7 - B3: ......Q- output pin offset voltage adjustment (refer to Table 9) B2 - B0: ......Not used Table 9 Ich and Qch Offset Adjustment Values
CR11 - B7 B6 B5 B4 B3 CR12 - B7 B6 B5 B4 B3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 Offset Voltage (mV) +45 +42 +39 +36 +33 +30 +27 +24 +21 +18 +15 +12 +9 +6 +3 0 CR11 - B7 B6 B5 B4 B3 CR12 - B7 B6 B5 B4 B3 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 Offset Voltage (mV) -3 -6 -9 -12 -15 -18 -21 -24 -27 -30 -33 -36 -39 -42 -45 -48
47/57
Semiconductor
MSM7584C
(17) CR18
B7 CR18 Initial Value -- 0 B6 -- 0 B5 -- 0 B4 -- 0 B3 LOCAL INV1 0 B2 LOCAL INV0 0 B1 -- 0 B0 -- 0
B7 - B4: ......Not used B3, B2: .......Local inversion mode setting bits (These bits are used when the demodulator side IF input is phase inverted in the system configuration) (0, 0): Normal mode (1, 1): Local inversion mode B1, B0: .......Not used (18) CR19
B7 CR19 Initial Value ADO7 0 B6 ADO6 0 B5 ADO5 0 B4 ADO4 0 B3 ADO3 0 B2 ADO2 0 B1 ADO1 0 B0 ADO0 0
B7 - B0: ......8bit output data from the RSSI-AD converter is written. The output results are listed in Table 10. Table 10
BBBBBBB 76543210 11111111 11111110 to 10000001 10000000 01111111 to 00000001 00000000 RSGAIN pin voltage (V) 2.1000 2.0945 to 1.4055 1.4000 1.3945 to 0.7055 0.7000
48/57
Semiconductor (19) CR20 (SRRI-ADC Offset Voltage Adjustment)
B7 CR20 Initial Value AD Offset4 0 B6 AD Offset3 0 B5 AD Offset2 0 B4 AD Offset1 0 B3 AD Offset0 0 B2 -- 0 B1 RS PDN 0
MSM7584C
B0 -- 0
B7 - B3: ......RSGAIN pin DC adjustment value (Table 11) Table 11
CR20 B7 B6 B5 B4 B3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 Adjustment Value (mV) 375 350 325 300 275 250 225 200 175 150 125 100 75 50 25 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 CR20 B7 B6 B5 B4 B3 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 Adjustment Value (mV) -25 -50 -75 -100 -125 -150 -175 -200 -225 -250 -275 -300 -325 -350 -375 -400
B1: .............. RSSI - ADC power down control 0: Power down 1: Power ON B2, B0: .......Not used
49/57
Semiconductor (20) CR21 (General I/O)
B7 CR21 Initial Value -- 0 B6 -- 0 B5 -- 0 B4 -- 0 B3 -- 0 B2 -- 0 B1 RO1 0
MSM7584C
B0 RO0 0
B7 - B2: ......Not used B1 - B0: ......Data written in B1 and B0 is output to the RO1 and RO0 pins. (21) CR22 (Control of Switches)
B7 CR22 Initial Value SW1 CONT 0 B6 SW2 CONT 0 B5 SW3 CONT 0 B4 SW4/5 CONT 0 B3 AOUT PDN 0 B2 AOUT3 CONT 0 B1 AOUT2 CONT 0 B0 AOUT1 CONT 0
B7, B6: .................... SW1, SW2 control 0: Open 1: Closed B5: ........................... SW3 control 0: Open 1: Closed B4: ........................... SW4/5 control 0: SW4 open, SW5 closed 1: SW4 closed, SW5 open B3: ........................... Sounder amplifier power down control 0: Power ON 1: Power down B2, B1, B0: .............. TOUT3 - 1 control 0: TOUT3 - 1 disabled 1: TOUT3 - 1 enabled Note: Set the unused bits of CR0 - CR22 to "0".
50/57
Semiconductor
MSM7584C
DATA CONFIGURATION IN THE EXTERNAL SERIAL REGISTER
X Address Space The address space of the external serial register is accessed based on (word direction indicated by the X address) (1 Kb depth in Y direction). The maximum X address in word direction depends on the total memory capacity of serial registers connected. Since the leading 32 words (32 Kb) of the serial register are used as the channel index area, X address 020h onward can be used as the voice data area.
CR5-B5 Total Memory Capacity (device name) Number of words X address* 0 1 Mb (MSM6389) 1K words 000h to 3FFh 1 4 Mb (MSM6684) 4K words 0000h to 0FFFh 1 8 Mb (MSM6685) 8K words 0000h to 1FFFh
* 0000h to 001Fh are used as the channel index area.
Y Address Space
For 1 Kb ADPCM data in Y direction, 4 bits 256 samples = 1024 bits are stored in the 1 Kb memory area. One Y address is allocated to one sample (4 bits) of ADPCM data and addressing is made with 00h to FFh.
X address (1 K words of 000h to 3FFh : 1 word = 1 Kb)
000h 01Fh 020h
3FFh
,
Channel index area (32 words 1 Kb + 32 Kb)
ADPCM (voice) data area 1 Kb in Y direction 1 word = 1 Kb Y address 01h 4 bit FEh 4 bit FFh 4 bit
1Mb serial register
00h
4 bit
Figure 16 Address Space of 1 Mb Serial Register
51/57
Semiconductor
MSM7584C
Channel Index Area of the Serial Register One channel (1 Kb) of the channel index area consists of the 40 bits of address data. (1) Stop Y address The Y address is represented by 8 bits and addressing is made with 00h to FFh. (2) Start X address, stop X address The X address is represented by 16 bits (valid 13 bits). If, for example, the serial register is 1Mb, the 1K-word X address space is addressed with 000h to 3FFh.
Address data
Blank data
40-bit 16-bit Start X address 8-bit Stop Y address 16-bit Stop X address
Start X address (ST0 to ST12)
ST0
ST1
ST11 ST12
--
--
--
Stop Y address (SPY0 to SPY7)
SPY0 SPY1
SPY6 SPY7
Stop X address (ST0 to SP12)
SP0
SP1
SP11 SP12
--
--
--
Figure 17 Channel Index Area of Serial Register
52/57
Semiconductor
MSM7584C
METHODS OF RECORDING AND PLAYBACK
Recording Method (See the flow chart in Figure 18) (1) * Set up the connection between the serial register/ voice ROM and ADPCM transmit-receive system. (See Figure 20) (CR5 - B7) N BUSY = 0? RPM = 0? * Specify the serial register/voice ROM. (CR5 B6) Y * Set the external capacity. (CR5 - B5) Basic setting * Set the NOP command. (CR5 - B1 = "0", B0 = "0") (2) * Set the start/stop address. (CR8 to CR12) (3) * Set the channel. (CR13 - B7 to B3) ST, SP * Set the ADWT (address write) instruction. (CR13 address setting - B1 = "0", B0 = "1") (4) * The start/stop address of the channel set by the Channel setting (ADWT) ADWT instruction is stored in the channel index area. When status register BUSY (CR7 - B1) changes from "1" to "0", storage is complete. N BUSY = 0? (5) * Start recording by setting the REC (recording) command (CR5 - B1 = "1", B0 = "0"). Y (6) * Check the recording start with the status register REC RPM bit (CR7 - B0 = "1"). (7) * To interrupt during recording, set the STOP (stop) command (CR5 - B1 = "1", B0 = "1"). N RPM = 1? In this case, to store the address counter contents in the channel index area as a new stop address, Y the following settings are required: * Set the channel. * Set the ADWT instruction. STOP * When the BUSY bit changes from "1" to "0", settings are complete. N (8) * When the address counter reaches the RPM = 0? stop address, recording is complete. Check completion of recording with Y RPM bit = "0". Channel setting
(ADWT) N
Recording
(1) CR5
(2) CR8 to 12
(3) CR13
(4) CR7
(5) CR5 Recording start (6) CR7 Recording start check
(7) CR5 Recording stop CR13 CR7
BUSY = 0? Y N RPM = 0? Y END (8) CR7 Recording completion check
Figure 18 Flow Chart of Recording
53/57
Semiconductor Playback Method (See the flow chart in Figure 19) (1) * Set up the connection between the serial register/voice ROM and ADPCM transmit-receive system. (See Figure 20) (CR5 B7) * Specify the serial register/voice ROM. (CR5 - B6) * Set the external capacity. (CR5 B5) * Set the NOP command. (CR5 B1 = "0", B0 = "0") (2) * Set the channel. (CR13 - B7 to B3) * Set the ADRD (address read) instruction. (CR13 - B1 = "1", B0 = "0") (3) * The start/stop address of the channel set by the ADRD instruction is fetched from the channel index area. When status register BUSY (CR7 - B1) changes from "1" to "0", fetching is complete. (4) * Start playback by setting the PLAY (playback) command (CR5 - B1 = "0", B0 = "1"). (5) * Check the playback start with the status register RPM bit (CR7 - B0 = "1"). (6) * To stop playback set the STOP command (CR5 - B1 = "1", B0 = "1"). (7) * When the address counter reaches the stop address, playback is complete. Check completion of playback with RPM bit = "0".
MSM7584C
Playback
N
BUSY = 0? RPM = 0? Y Basic setting Channel setting (ADRD) (1) CR5
(2) CR13
N
BUSY = 0? Y PLAY
(3) CR7
(4) CR5 Playback start (5) CR7 Playback start check
N
RPM = 1? Y
STOP
(6) CR5 Playback stop
N
RPM = 1? Y END
(7) CR7 Playback completion check
Figure 19 Flow Chart of Playback
54/57
Semiconductor
MSM7584C
SIGNAL FLOW IN RECORDING/PLAYBACK
When the serial register is connected to each ADPCM transmitter and receiver, the flow of recording/playback signal is as follows:
Transmit-side recording (CR5 - B7 = "1" + REC)
IS(ADPCM-OUT)
Transmit-side playback (CR5 - B7 = "1" + PLAY)
IS(ADPCM-OUT)
A-IN
ADPCM CODER
A-IN
ADPCM CODER
Serial register
Serial register
Receive-side recording (CR5 - B7 = "0" + REC)
IR (ADPCM-IN)
Receive-side playback (CR5 - B7 = "0" + PLAY)
IR (ADPCM-IN)
A-OUT
ADPCM DE-CODER
A-OUT
ADPCM DE-CODER
Serial register
Serial register
Figure 20 Signal Flow in Transmit/Receive Side Recording/Playback
55/57
1 Mbit Serial Register MSM6389 DIN DOUT WE SAD SAS TAS RWCK SADX SASX TAS RDCK SASY DOUT
Semiconductor
Ringer output
1 Mbit Serial Voice ROM MSM6595-XXX
41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60
R1
APPLICATION CIRCUIT
DIO RWCK TAS SAS SAD WE RO0 RO1 TOUT3 TOUT2 TOUT1 IO7 IO6 IO5 VDDC IO4 IO3 IO2 IO1 GSX
C1
R1
SADY TEST TEST CS
Transmit side voice analog input C2
AU/D RS/A RFSH AM TEST CS
R1 Control Register Control Signal Reset C4
* A 1 Mbit serial register and a 1 Mbit serial voice ROM are used.
Receive side voice analog input
R1
Speaker input
C2 C3
MSM7584CTS-K
Master Clock Input 8 kHz Sync Signal Input Receive Side VOX Input Transmit Side VOX output
C3
RSSI input
R1
R1
Modulator I component output To quadrature modulator Modulator Q component output
61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 Voice Mute Control Signal Bit Clock Input Transmit Side ADPCM Output R2 VDD
AIN- AIN+ SGCT AGC SAO VFRO PWI AOUT- AOUT+ SGCR SGM AGM SGRS RSSI RSGAIN I+ I- Q+ Q- VDDM 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21
CS1 CS2 DOUT DIN DEN EXCK RESET MCK DGC SYNC VOXO VOXI MLV0 MLV1 MLV2 RXMUTE BCLK PCMSI PCMSO IS
IR PCMRI PCMRO DGM IFIN TXCI TXCO TXD TXW BSTO RXSC RXD RXC RPR AFC/RCW SLS PDN3 PDN2 PDN1 PDN0
20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
VDD
C4
VDDM, VDDC
1 mF
Receive side ADPCM input
Modulator input data Modulator data window Modulator burst position output Receive symbol clock output Receive data output Receive clock output
Demodulator control signal
Power down control signal
Demodulator IF input Modulator input clock
DGM, DGC, AGM, AGC
+ 10 mF -
MSM7584C
56/57
C1 = 1 mF, C2 = 10 + 0.1 mF C3 = 0.1 mF, C4 = 1000 pF R1 = 27 kW, R2 = 510 W
Semiconductor
MSM7584C
PACKAGE DIMENSIONS
(Unit : mm)
TQFP80-P-1212-0.50-K
Mirror finish
Package material Lead frame material Pin treatment Solder plate thickness Package weight (g)
Epoxy resin 42 alloy Solder plating 5 mm or more 0.40 TYP.
Notes for Mounting the Surface Mount Type Package The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact Oki's responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times).
57/57

▲Up To Search▲

Price & Availability of MSM7584CTS-K

	To Download MSM7584CTS-K Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .